1. Field of the Invention
This invention relates to a semiconductor integrated circuit device having a dynamic type random access memory (which is hereinafter referred to as DRAM) contained therein, and more particularly to an operation mode setting circuit, which may be used for a memory integrated circuit device of an image process circuit, for example, for setting the operation mode of the DRAM in response to a CAS (column address strobe) signal received before the input of a RAS (row address strobe) signal.
2. Description of the Related Art
Recently, there is a tendency to incorporate various functions into a single memory integrated circuit device to attain multi-function modes. For example, in the case of DRAM integrated circuit devices of one-bit output configuration, RAS, CAS and WE (write enable) signals are used as control signals. When a combination of these control signals is used to set the operation mode, it is possible to determine the subsequent operation mode of the memory by use of the CAS and WE signal conditions which are set at the time of fall of the RAS signal. In this case, it is theoretically possible to set 2.sup.2 =4 different types of modes. However, it is necessary to consider the following matter as a problem inherent to the DRAM. In general, a mode in which the CAS signal is set at a low level (active level), at the time of fall of the RAS signal, is used as an auto-refresh mode, and in this mode, the refresh operation is effected according to a row address generated from a counter in the memory. In the refresh mode, no column address is necessary and it is not necessary to fetch an external address according to the CAS signal. Therefore, when the CAS signal is thus set at the low level, it is generally difficult to specify an operation mode in which a column address or row address from the exterior is required.
Recently, however, memories having serial successive input/output ports have been developed as image processing memory integrated circuit devices, and with this memory development, various modes in which specification of the column address is not required have been provided. For example, since the contents of a group of memory cells specified by a single row address are collectively transferred in each operation of data transfer between the serial input/output section and memory section, the column address is not required. Further, since the contents of a group of memory cells specified by a single row address are written at the same time in the flash write mode corresponding to a high-speed image clearing mode or the like, the column address is not required. Therefore, there is a possibility that the mode for inputting the CAS signal before the RAS signal (which is known as the CAS-before-RAS mode) is used for selectively setting function mode other than the auto-refresh mode. For this reason, even in the multifunction mode memory, mode specification is effected by the CAS-before-RAS operation in function modes in which no column address is used, and it is desired to keep those function modes in which the CAS signal is set at a high level so that the function modes requiring the column address can be selectively set. In this case, there occurs a problem concerning the timing relation between the row address generated from the counter provided in the memory and the row address externally supplied. Now, the problem is explained in detail with reference to FIGS. 1 and 2.
As shown in FIG. 1, an external address signal and an internal address signal (generated from the counter in the device) are supplied to address buffer circuit 11. The operation of address buffer circuit 11 is controlled by the RAS and CAS signals. An output of address buffer circuit 11 is supplied to word line selection/driving circuit 12.
With the circuit construction shown in FIG. 1, when the row address included in an external address is fetched at the time of fall of the RAS signal, set-up time t.sub.ASR and hold time t.sub.RAH of the external address are precisely determined with respect to the time of fall of the RAS signal as shown in FIG. 2. Therefore, in the auto-refresh mode in which the internal address is fetched, it is necessary to fully shift or change the levels of the external address and internal address during the time between the beginning of set-up time t.sub.ASR and the end of hold time t.sub.RAH. In order to meet this requirement, set-up time t.sub.CSR of the CAS signal in the case of setting the CAS-before-RAS mode is set to be longer than the minimum value t.sub.ASRmin of set-up time t.sub.ASR. As a result, it becomes possible to determine whether the circuit is in the auto-refresh mode or not before the row address is fetched. Therefore, address buffer circuit 11 can select one of the external and internal addresses to be fetched during the time of set-up time t.sub.ASR and hold time t.sub.RAH. Further, it will not take additional time to effect data transfer from address buffer circuit 11 to word line selection/driving circuit 12 in comparison with the memory system having no auto-refresh mode.
However, in a case where an operation mode which requires the external address and is different from the auto-refresh mode is specified by the CAS-before-RAS operation, the mode specification cannot be effected only by detection of a high or low level of the CAS signal. This problem commonly occurs in semiconductor integrated circuit devices (DRAM integrated circuit device, image processing memory integrated circuit device and the like) having a DRAM which requires the operation of specifying an operation mode other than the auto-refresh mode by use of the CAS-before-RAS operation.
Further, in a mode other than the CAS-before-RAS mode, it is desired that the timings applicable to the conventional DRAM can be set. This is because a semiconductor integrated circuit device additionally having the DRAM mode can be attained without providing an additional circuit or changing the memory system.